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lcd panel timing controller (15") CS5842 century semiconductor inc. block diagram general description features (continued) features usa: 1485 saratoga ave. #200 san jose, ca, 95129 tel: 408-973-8388 fax: 408-973-9388 sales@century-semi.com sales@century-semi.com.tw www.century-semi.com rev.0.2 october 2000 page 1 of 25 century semiconductor, inc. taiwan: no. 2, industry east rd. 3rd, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 ? interface (5v/3.3v[cmos] input, 3.3v[cmos] out- put) ? single (xga2: 65mhz)/dual (xga: 32.5mhz) 8-bit data input; dual port 8-bit output; sxga auto detective ? timing adjustable for horizontal clock output ? correspondent to control timing & specific resolu- tion for different driver ic by changing a mask: 1. can vary the pulse width & starting position of lp signal and pol signal polarity position changed along with lp signal 2. can vary the pulse width & starting position of clkv signal and tgs time ? control asic output timing design is based on data enable signals ? embedded power on reset circuits, vth=2.1v, tol- erance 0.3v ? esd spec. 4kv ? power on latch up 200ma/6.6v ? single 3.3v supply ? 144-pin lqfp package CS5842 is a tft-lcd timing controller, which is applicable to 8-bit data xga (1024*768), sxga (1280*1024). CS5842 can update the response timing for display mode of xga and sxga automatically. CS5842 provides a selectable polarity check function to inverse output data for emi reducing, when the toggle number of odd/even rgb outputs is larger than 13. dena vd hd dclk1 inv pndclk pnvd polin dataht sxmd pnhms plmd set test clkht gt(2~1) oddri(7~0) oddgi(7~0) oddbi(7~0) pnhd icmd(2~1) scmd evenri(7~0) evengi(7~0) evenbi(7~0) clkv stv1 stv2 clkh sth8 pol rlsc lp shc sth1 power on reset pol/shc generator clkv generator lp generator clkh generator delay sample polarity output selector data-path oddgo(7~0) evengo(7~0) oddro(7~0) evenro(7~0) oddbo(7~0) evenbo(7~0) hms1 sth1/sth8 generator stv1/stv3 generator rgbd input selector hms2 CS5842
CS5842 century semiconductor inc. page 2 of 25 pin connection diagram figure-1 144-pin lqfp 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd test evengi7 evengi6 evengi5 evengi4 evengi3 evengi2 evengi1 evengi0 evenri7 evenri6 evenri5 evenri4 evenri3 evenri2 evenri1 evenri0 clkht icmd1 icmd2 plmd pndclk pnhms scmd evenbo7 evenbo6 evenbo5 evenbo4 evenbo3 evenbo2 evenbo1 evenbo0 evengo7 evengo6 vdd vdd inv hd vd dena dataht dclk1 gnd pnhd pnvd sxmd gt1 gt2 set rlsc stv1 stv3 clkv sth1 lp hms1 hms2 pol shc sth8 oddro0 oddro1 oddro2 oddro3 oddro4 oddro5 oddro6 oddro7 oddgo0 oddgo1 vdd gnd gnd evengo5 evengo4 evengo3 evengo2 evengo1 evengo0 evenro7 evenro0 evenro5 evenro2 evenro3 evenro4 evenro1 evenro6 polin gnd clkh gnd oddbo7 oddbo6 oddbo5 oddbo4 oddbo3 oddbo2 oddbo1 oddbo0 oddgo7 oddgo6 oddgo5 oddgo4 oddgo3 oddgo2 gnd gnd gnd gnd evenbi0 evenbi1 evenbi2 evenbi3 evenbi4 evenbi5 evenbi6 evenbi7 oddri0 oddri1 oddri2 oddri3 oddri4 oddri5 oddri6 oddri7 oddgi0 oddgi1 oddgi2 oddgi3 oddgi4 oddgi5 oddgi6 oddgi7 oddbi0 oddbi1 oddbi2 oddbi3 oddbi4 oddbi5 oddbi6 oddbi7 gnd gnd CS5842 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
CS5842 century semiconductor inc. page 3 of 25 pin description name i/o pin block type description note vdd 1 supply 3.3v 10% test i 2 p5inphu test pin, usually open open evengi(7-0) i 3-10 p5inpmn even green pixel data input. (evengi0: lsb, evengi7:msb) (dclk1 synchronized; low as xga2 mode.) xga:16.25mhz 5v tolerant evenri(7-0) i 11-18 p5inpmn even red pixel data input. (evenri0: lsb, evenri7: msb) (dclk1 synchronized; low as xga2 mode.) xga:16.25mhz 5v tolerant clkht i 19 p5inphu adjust clkh timing output. 1. clkht=low, 0.0ns delay 2. clkht=open, 3.3ns delay 20k ? pull up (clkht:0 ? ) icmd(1-2) i 20-21 p5inphu source driver ic selection (icmd:lsb, icmd2:msb) 1. icmd2 = open, icmd1 = low, (10): ic1 (nec pd16750, hitachi hd66350t) 2. icmd2 = open, icmd1 = open, (11): ic2 (toshiba t6l64c, sharp lh168r) 3. icmd2 = low, icmd1 = low, (00): ic3 (winbond wfp6815) 4. icmd2 = low, icmd1 = open, (01): ic4 (t.i.tms57571) 20k ? pull up (icmd1:0 ? icmd2:open) plmd i 22 p5inphu polarity invert signal. 1. plmd = open: two line inverted 2. plmd = low: one line inverted 20k ? pull up (0 ? ) pndclk i 23 p5inphu input clock signal polarity switch input. low = inverted open = non-inverted 20k ? pull up (open) pnhms i 24 p5inphu hms input invert switch output. open = non-inverted low = invert output signal of hms1 and hms2. 20k ? pull up (0 ? ) scmd i 25 p5inphd controlling pin of driver ic r/l pin open: rlsc = high ? output stv1, sth1; stv3, sth8: no output (low) high: rlsc = low ? output stv3, sth8; stv1, sth1: no output (low) evenbo(7-0) o 26-33 p3outrb even blue pixel output (evenbo0:lsb, evenbo7:msb) xga:16.25mhz evengo(7-6) o 34-35 p3outrb even green pixel output (evengo0:lsb, evengo7:msb) xga:16.25mhz vdd 36 power 3.3v 10% gnd 37 ground. gnd 38 ground.
CS5842 century semiconductor inc. page 4 of 25 evengo(5-0) o 39-44 p3outrb even green pixel output (evengo0:lsb, evengo7:msb) xga:16.25mhz evenro7 o 45 p3outrb even red pixel output (evenro7:msb) xga:16.25mhz evenro0 o 46 p3outrb even red pixel output (evenro0:lsb) xga:16.25mhz evenro5 o 47 p3outrb even red pixel output xga:16.25mhz evenro2 o 48 p3outrb even red pixel output xga:16.25mhz evenro3 o 49 p3outrb even red pixel output xga:16.25mhz evenro4 o 50 p3outrb even red pixel output xga:16.25mhz evenro1 o 51 p3outrb even red pixel output xga:16.25mhz evenro6 o 52 p3outrb even red pixel output xga:16.25mhz polin i 53 p5inphu hms polarity function calculation switch set. 1. polin = open: calculated; hms1, hms2 calculated separately. 2. polin = low: un-calculated; hms1 = hms2 = inv 20k ? pull up (open) gnd 54 ground clkh o 55 p3outrd shift clock output used by source driver ic. xga:32.25mhz gnd 56 ground oddbo(7-0) o 57-64 p3outrb odd blue pixel output. (oddbo0: lsb, oddbo7: msb) xga:16.25mhz oddgo(7-2) o 65-70 p3outrb odd green pixel output. (oddgo0: lsb, oddgo7: msb) xga:16.25mhz gnd 71 ground gnd 72 ground vdd 73 supply 3.3v 10% oddgo(1-0) o 74-75 p3outrb odd green pixel output. (oddgo0: lsb; oddgo7: msb) xga:16.25mhz oddro(7-0) o 76-83 p3outrb odd red pixel output. (oddro0: lsb; oddro7: msb) xga:16.25mhz sth8 o 84 p3outrb start pulse (s8 s1) of source driver ic shc o 85 p3outrb signal for t.i. pol o 86 p3outrb polarity invert signal of source driver ic hms(2-1) o 87-88 p3outrb data polarity invert control signal output. output is based on polin set. lp o 89 p3outrb latch pulse of source driver ic. name i/o pin block type description note
CS5842 century semiconductor inc. page 5 of 25 sth1 o 90 p3outrb start pulse (s1 s8) of source driver ic. clkv o 91 p3outrb shift clock output for gate driver ic. stv3 o 92 p3outrb start pulse (g3 g1 ) of gate driver ic. stv1 o 93 p3outrb start pulse (g1 g3 ) of gate driver ic. rlsc o 94 p3outrb r/l output for source driver ic. set i 95 p5inphu asic internal reset setting. low = initialization, is usually open. 20k ? pull up (open) gt(2-1) i 96-97 p5inphu adjust clkv clock timing (gt1: lsb; gt2: msb). 20k ? pull up (gt1:open gt2:0 ? default: 01 ? 3 s) 1. icmd2 = open, icmd1 = low: ic1 clkv rising edge generated before lp falling edge. 4 steps: 0.5 s (i.e. 17clkh) each step, 2.5~4.0 s 2. icmd2 = open, icmd1 = open: ic2 clkv rising edge generated before lp rising edge. 4 steps: 0.5 s (i.e. 17clkh) each step, 2.5~4.0 s 3. icmd2 = low, icmd1 = low: ic3 clkv rising edge generated before lp falling edge. 4 steps: 0.5 s (i.e. 17clkh) each step, 2.5~4.0 s 4. icmd2 = low, icmd1 = open: ic4 clkv rising edge generated before lp falling edge. 4 steps: 0.5 s (i.e. 17clkh) each step, 2.5~4.0 s sxmd i 98 p5inphu xga/xga2 switch selection sxmd = open; xga(32.5mhz) sxmd = low; xga2(65mhz) 20k ? pull up (open) pnvd i 99 p5inphu vertical sync signal polarity setting. low = inverted; open = non-inverted. 20k ? pull up (open) pnhd i 100 p5inphu horizontal sync signal polarity setting. low = inverted; open = non-inverted. 20k ? pull up (open) gnd 101 ground dclk1 i 102 p5inpmn dot clock input. xga: 32.5mhz 5v tolerant dataht i 103 p5inphu adjust data output timing 1. dataht = open 0.0ns/2.2ns/3.2ns delay 2. dataht = low 0.0ns/2.2ns/4.4ns delay 20k ? pull up (open) dena i 104 p5inpmn data enable signal input. dclk1 synchronized. 5v tolerant vd i 105 p5inpmn vertical sync signal input. dclk1 synchronized. 5v tolerant hd i 106 p5inpmn horizontal sync signal input. dclk1 synchronized. 5v tolerant inv i 107 p5inpmn data input of polarity control. high = polarity of input data been inverted. low = polarity of input data not been inverted. 5v tolerant name i/o pin block type description note
CS5842 century semiconductor inc. page 6 of 25 vdd 108 supply 3.3v 10%. gnd 109 ground gnd 110 ground oddbi(7-0) i 111- 118 p5inpmn odd blue pixel data input. (oddbi0: lsb; oddbi7: msb) dclk1 synchronized xga:16.25mhz 5v tolerant oddgi(7-0) i 119- 126 p5inpmn odd green pixel data input. (oddgi0: lsb; oddgi7: msb) dclk1 synchronized xga:16.25mhz 5v tolerant oddri(7-0) i 127- 134 p5inpmn odd red pixel data input. (oddri0: lsb; oddri7: msb) dclk1 synchronized xga:16.25mhz 5v tolerant evenbi(7-0) i 135- 142 p5inpmn even blue pixel data input. (evenbi0: lsb; evenbi7: msb) (dclk1 synchronized; low as xga2 mode.) xga:16.25mhz 5v tolerant gnd 143 ground gnd 144 ground name i/o pin block type description note
CS5842 century semiconductor inc. page 7 of 25 operating environment maximum operating frequency: 80mhz clock duty: 50 10% voltage range: 3.3 0.3v operating temperature range: -40~85 c (storage temperature range: -65~150 c).
CS5842 century semiconductor inc. page 8 of 25 electrical characteristics 1. absolute maximum ratings: note: the component will be damaged if exceed the absolute maximum condition. normal function operating condition is as below: 2. normal operating condition: note: under normal operation, the function of asic ic must be normal; schmitter buffer is the buffer of hysteresis characteristic. symbol parameter condition range unit v dd power -0.5 ~ +4.6 v v i signal input voltage 5v tolerant buffer -0.5 ~ +4.6 & v 1 < v dd +0.5 v v i signal input voltage 5v tolerant buffer -0.5 ~ +6.6 & v 1 < v dd +3.0 v v o signal output voltage output buffer -0.5 ~ +4.6 & v 1 < v dd +0.5 v i o signal output current i ol = 6ma type 20 ma i o signal output current i ol = 8ma type 30 ma i o signal output current i ol = 12ma type 40 ma t a operating ambient -40 ~ +85 c t stg storage temperature -65 ~ +150 c symbol parameter condition min typ max unit v dd power 3.0 3.3 3.6 v t a operating ambient -40 85 c v ih high level input voltage 5v tolerant buffer 2.0 v dd v v il low level input voltage 5v tolerant buffer 0 0.8 v v p positive trigger voltage 5v tolerant schmitter buffer 1.40 2.40 v v n negative trigger voltage 5v tolerant schmitter buffer 0.8 1.6 v v h hysteresis voltage 5v tolerant schmitter buffer 0.3 1.5 v v ih high level input voltage 5v tolerant buffer 2.0 5.5 v v il low level input voltage 5v tolerant buffer 00.8v tri input rising time normal input 0 200 ns tfi input falling time normal input 0 200 ns tri input rising time schmitter input 010ms tfi input falling time schmitter input 010ms
CS5842 century semiconductor inc. page 9 of 25 3. dc characteristic (t a = -40 c ~ +85 c, v dd = 3.3v 0.3v; (t j = -40 c ~ +125 c)) note: 1. impedance of pull-up and pull-down depend on input voltage and output voltage. symbol parameter condition min typ max unit i dos v i = v dd or gnd 3340 a i oz off state output current v o = v dd or gnd - 10 a i os output short current v o = 0v - -250 ma i l input leakage current v o = v dd or gnd - 1.0 a i l input leakage current v i = gnd (pull-up 20k ?) -67 -165 -360 a i l input leakage current v i = v dd (pull-down 20k ?) 67 165 360 a r pu pull up resistance (20k ?) (note1) v i = gnd 102045k ? r pd pull down resistance (20k ?) (note1) v i = v dd 10 20 45 k ? i ol output low current v ol = 0.4v (i ol = 6.0 ma type) 6.0 - - ma i ol output low current v ol = 0.4v (i ol = 8.0 ma type) 8.0 ma i ol output low current v ol = 0.4v (i ol = 12.0 ma type) 12.0 ma i oh output high current v oh = 2.4v (i ol = 6.0 ma type) -6.0 ma i oh output high current v oh = 2.4v (i ol = 8.0 ma type) -8.0 ma i oh output high current v oh = 2.4v (i ol = 12.0 ma type) -12.0 ma v ol low level input voltage i ol = 0 ma 0.1 v v oh high level input voltage i ol = 0 ma v dd -0.1 v
CS5842 century semiconductor inc. page 10 of 25 4. i/o buffer block type i/o description p5inphu i(input) 5v tolerant input buffer (schmitt in) with pull-up resistance 20k ? p5inpmn i(input) 5v tolerant input buffer p5inphd i(input) 5v tolerant input buffer (schmitt in) with pull-down resistance 20k ? p3outrb o(output) output buffer (low noise: i ol = 8ma) p3outrd o(output) output buffer (i ol = 12ma)
CS5842 century semiconductor inc. page 11 of 25 input timing specification note: high, low level of input signal: v il = 0.8v, v ih = 2.2v. symbol item specification unit min typ max f(dclk1) input clock frequency 30 32.5 54/80 mhz tw(dclk1) input clock period 12.5 30.8 33.3 ns twh(dclk1) input clock high time 0.3 - - clk twl(dclk1) input clock low time 0.3 - - clk tst(di) input data setup time 2.3 - - ns thd(di) input data hold time 7.3 - - ns tst(dena) input data enable signal setup time 2.3 - - ns thd(dena) input data enable signal hold time 7.3 - - ns tst(hd) horizontal sync signal setup time 2.3 - - ns thd(hd) horizontal sync signal hold time 7.3 - - ns tst(vd) vertical sync signal setup time 2.3 - - ns thd(vd) vertical sync signal hold time 7.3 - - ns tw(dena) input data enable signal high time 512 512 640 clk tbh(denah) input data enable horizontal sync signal blanking time 6- -clk f(hd) horizontal sync signal - 48.25 62.5 khz tw(hd) hd horizontal sync signal low time 1 - - clk tf(hd) horizontal front porch 0 - - clk tb(hd) horizontal back porch 6 - - clk tbh(denav) input data enable horizontal sync signal blanking time 4- -h f(vd) vertical sync signal 55 60 75 hz tw(vd) vd vertical sync signal low time 1 - - h tf(vd) vertical front porch 0 - - h tb(vd) vertical back porch 4 - - h
CS5842 century semiconductor inc. page 12 of 25 figure-2 figure-3 twl(dclk1) twh(dclk1) dclk1 ri,gi,bi tst(di) thd(di) invalid data data tst(dena) thd(dena) dena tw(dclk1) thd(di) tst(di) invalid data data dclk1 tst(dena) thd(dena) dena twl(dclk1) twh(dclk1) tw(dclk1) ri,gi,bi
CS5842 century semiconductor inc. page 13 of 25 figure-4 dclk1 vd dclk1 hd thd(vd) tw(vd) vd tst(vd) thd(hd) tst(hd) tf(vd) tb(vd) tbh(denav) dena tw(hd) tf(hd) tb(hd) tbh(denah) hd dena tw(dena)
CS5842 century semiconductor inc. page 14 of 25 horizontal output specification 1-1 icmd1 = low --(nec pd16750, hitachi hd66350t) pndclk, pnhvd = open, icmd2 = open figure-5 tgs: 2.5 ~ 4 s (0.5 s pitch) pol: plmd = l, revert once per hd plmd = h, revert once per 2hd revert once per vd horizontal output specification 1-2 icmd1 = open--(toshiba t6l64c, sharp lh168r) pndclk, pnhvd = open, icmd2 = open figure-6 tgs: 2.5 ~ 4 s (0.5 s pitch) pol: plmd = l, revert once per hd plmd = h, revert once per 2hd revert once per vd clkh last 512 blanking data 1 clkh 2.5 s (85 clkh) tgs ro.go.bo (each 8bits) hms sth lp pol clkv 1 2 1 3.5 clkh 1 s (34 clkh) clkh last 512 blanking data 1 clkh 3 clkh tgs ro.go.bo (each 8bits) hms sth lp pol clkv 1 2 1 1.5 clkh 1 s (34 clkh)
CS5842 century semiconductor inc. page 15 of 25 horizontal output 1-3 icmd1 = low-- (winbond wfp6815) pndclk, pnhvd = open, icmd2 = low figure-7 tgs: 2.5 ~ 4 s (0.5 s pitch) pol: plmd = l, revert once per hd plmd = h, revert once per 2hd revert once per vd horizontal output 1-4 icmd1 = open--( ti tms57571b ) pndclk, pnhvd = open, icmd2 = low figure-8 tgs: 2.5 ~ 4 s (0.5 s pitch) pol: plmd = l, revert once per hd plmd = h, revert once per 2hd revert once per vd shc: revert once per hd only clkh last 512 blanking data 1 clkh 5 clkh (tgs+0.5clkh) ro.go.bo (each 8bits) hms sth lp pol clkv 1 2 1 1 clkh ? 1 s (34.5 clkh) clkh last 512 blanking data 1 clkh 2 s (68 clkh) tgs ro.go.bo (each 8bits) hms sth lp pol, clkv 1 2 1 2.5 clkh 5 s (170 clkh) shc
CS5842 century semiconductor inc. page 16 of 25 horizontal output 2-1 (data output specification) icmd1 = low-- (nec pd16750, hitachi hd66350t) , icmd2 = open figure-9 symbol item specification unit min typ max tw clk pulse width 14 ns twh clk high pulse width 3 ns twl clk low pulse width 3 ns tst1 data setup time 1 ns thd1 data hold time 2 ns tst2 sth setup time 1 ns thd2 sth hold time 2 ns tst3 clk-lp time 6 ns thd3 lp-clk time 6 tw clkh tst2 thd2 data1 70% v dd 30% v dd twh twl data2 blanking data thd1 tst1 thd3 2 s above 2 clk above output data (hms1,hms2) sth clkh output data lp data (last) tst2 thd2 tst3
CS5842 century semiconductor inc. page 17 of 25 horizontal output 2-2 (data output specification) icmd1 = open-- (toshiba t6l64c, sharp lh168r) ,icmd2 = open figure-10 symbol item specification unit min typ max twh clk high pulse width 4 ns twl clk low pulse width 4 ns tst1 data setup time 4 ns thd1 data hold time 0 ns tst2 sth setup time 4 ns thd2 sth hold time 0 ns tst3 clk-lp time 4 ns tw clkh tst2 thd2 data1 60% v dd 40% v dd twh twl data2 blanking data thd1 tst1 tst3 2 clk above 1 clk above output data (hms1,hms2) sth clkh output data lp data (last) tst2 thd2
CS5842 century semiconductor inc. page 18 of 25 horizontal output 2-3 (data output specification) icmd1 = low-- (winbond wfp6815) , icmd2 = low figure-11 symbol item specification unit min typ max twh clk high pulse width 6 ns twl clk low pulse width 6 ns tst1 data setup time 3 ns thd1 data hold time 0 ns tst2 sth setup time 3 ns thd2 sth hold time 0 ns tst3 lp setup time 10 ns thd3 lp hold time 2 tclk tw clkh tst2 thd2 data1 70% v dd 30% v dd twh twl data2 blanking data thd1 tst1 thd3 tst3 output data (hms1,hms2) sth clkh output data lp data (last) tst2 thd2
CS5842 century semiconductor inc. page 19 of 25 horizontal output 2-4 (data output specification) icmd1 = open-- (ti tms 57571b) , icmd2 = low figure-12 symbol item specification unit min typ max tw clk pulse width 18 ns twh clk high pulse width 4 ns twl clk low pulse width 4 ns tst1 data setup time 4 ns thd1 data hold time 0 ns tst2 sth setup time 4 ns thd2 sth hold time 0 ns tst3 clk-lp time 4.5 s thd3 shc hold time 4.5 s tw clkh tst2 thd2 data1 70% v dd 30% v dd twh twl data2 blanking data thd1 tst1 1.5 s above 1 clk above output data (hms1,hms2) sth clkh output data lp data (last) 70% v dd 30% v dd tst3 thd3 lp shc (only one line) pol (one line/two lines)
CS5842 century semiconductor inc. page 20 of 25 vertical output 3-1 (data output specification ) (nec pd16750, hitachi hd66350t, toshibi t6l34c, sharp lh168r, winbond wfp6815) figure-13 1 vd vd 1 2 3 4 767 1 hd 767 768 769 1 hd hd dena stv clkv 768 1 pol 767 768 2 1 hd 10 s (330 clkh) stv clkv
CS5842 century semiconductor inc. page 21 of 25 vertical output 3-2 (data output specification ) (t.i. tms57571) figure-14 1 vd vd 1 2 3 4 767 1 hd 766 1 hd 10 s (330 clkh) stv clkv hd dena stv clkv 768 1 lp 767 768 2 1 hd 767 768 769 2 1 1 2 768 769 pol, shc
CS5842 century semiconductor inc. page 22 of 25 clkv, stv timing specification figure-15 symbol item specification unit min typ max tst(stv) stv set-up time 1 s thd(stv) stv hold time 1 s tw(clkv) clkv period 8 s twh(clkv) clkv high width 3.5 s twl(clkv) clkv low width 3.5 s twl(clkv) clkv tst(stv) thd(stv) stv twh(clkv) tw(clkv)
CS5842 century semiconductor inc. page 23 of 25 data polarity figure-16 above polarity diagram indicates the relationship between hms and odd/even data output is related to pin "polin". 1. polin = low; polarity function is disable. hms1, 2 output are inv; rgb data output is the same as rgb input data. 2. polin = open; polarity function is enable. ? asic will compare odd data (1a) of number "n" with odd data (3) of number "n+1": ? as the number of bits changed exceeds 13, hms1 (data3) output high and odd data (3a) outputs are inversion of odd data(3). ? as the number of bits changed is below 13, hms1 (data3) output low and odd data (3a) outputs are odd data (3). ? asic will compare even data (2a) of number "n" with even data (4) of number "n+1": ? as the number of bits changed exceeds 13,hms2 (data4) output high and even data (4a) outputs are inversion of even data(4). ? as the number of bits changed is below 13, hms2 (data4) output low and even data (4a) outputs are even data (4). 2 4 6 dclk1 even data (24 bits) even n data (24 bits) bit number changed for even & odd output data nn+1 1 3 5 odd data (24 bits) 2a 4a 6a 1a 3a 5a data2 data4 data6 data1 data3 data5 bit number changed for even & odd output data odd n data (24 bits) hms2 output hms1 output
CS5842 century semiconductor inc. page 24 of 25 package outline (144-pin lqfp) symbol dimensions in millimeters dimensions in inches min nom max min nom max a - - 1.60 - - 0.063 a1 0.05 - - 0.002 - - a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.12 - 0.20 0.005 - 0.008 d 21.85 22.00 22.15 0.860 0.866 0.872 d1 19.90 20.00 20.10 0.783 0.787 0.791 e 21.85 22.00 22.15 0.860 0.866 0.872 e1 19.90 20.00 20.10 0.783 0.787 0.791 e - 0.50 - - 0.020 - l 0.45 0.60 0.75 0.018 0.024 0.030 l1 - 1.00 - - 0.039 - 03.57 03.57 l l1 eb a1 a c a2 d d1 1 36 72 73 108 109 144 e e1 37
CS5842 century semiconductor inc. page 25 of 25 application circuit schematic figure-17 using 144-pin lqfp stv3 oro2 r61 22 ogi4 c1 470u obi0 r77 22 vd ero2 r59 22 ebi7 r41 22 ori6 ogo7 eri4 ero1 c7 .1u r85 22 ero0 r33 22 r99 22 ebo0 r81 22 pnvd ero5 ogo2 obo1 r37 22 sth8 r26 22 r23 22 eri0 eri3 clkht ego2 obo4 r19 22 r30 22 ebo5 inv r15 22 egi5 r72 22 ebi3 ero7 ego1 r53 22 r51 22 ebi5 ogo5 r12 22 r114 22 r47 22 ogi6 obo5 r105 22 r78 22 r38 22 obi6 r50 22 r116 22 r67 22 r48 22 r40 22 r25 22 ogi0 ego4 r103 22 r117 22 egi2 r14 22 r74 22 gt2 ebi2 obi2 eri7 obo7 r13 22 r70 22 r5 22 r86 22 r102 22 v3.3d obi4 ori4 r56 22 r113 22 r128 22 ego3 sth1 ogo3 r98 22 oro1 r39 22 r4 22 r73 22 obo6 ori7 oro0 ero6 set r115 22 oro5 r94 22 egi6 ogi5 ebi1 j1 5v in 1 2 oro4 r96 22 clkv eri5 obi7 oro6 ebi0 icmd2 r123 22 lp r7 22 u1 lt1086 3 1 2 vin adj vout r106 22 eri2 plmd ori5 ego5 r6 22 r107 22 r93 22 r125 22 r21 22 r43 22 r62 22 r65 22 dena ori0 r34 22 r83 22 ebi4 r8 22 r22 22 ebo4 oro3 obo0 r75 22 r1 22 pnhms ori3 r24 22 v3.3d ego6 ogo0 r89 22 r84 22 r120 22 c4 0.1u r9 22 r124 22 egi4 ogi2 r80 22 ebo2 dclk1 ero3 r58 22 r11 22 r88 22 ebo6 r28 22 r29 22 pndclk egi3 r100 22 r3 22 ego0 egi1 stv1 r111 22 hd r91 22 v5.0 egi7 r17 22 r127 22 c3 100u icmd1 obi3 obo3 eri6 r108 22 ero4 r104 22 sxmd dadht obo2 r27 22 r69 22 pol shc gt1 r79 22 c8 .1u r121 22 r71 22 r82 22 r45 22 r119 22 ebo1 pnhd ebo3 rlsc CS5842 u2 CS5842 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 vdd test egi7 egi6 egi5 egi4 egi3 egi2 egi1 egi0 eri7 eri6 eri5 eri4 eri3 eri2 eri1 eri0 clkht icmd1 icmd2 plmd pndclk pnhms scmd ebo7 ebo6 ebo5 ebo4 ebo3 ebo2 ebo1 ebo0 ego7 ego6 vdd gnd gnd ego5 ego4 ego3 ego2 ego1 ego0 ero7 ero0 ero5 ero2 ero3 ero4 ero1 ero6 polin gnd clkh gnd obo7 obo6 obo5 obo4 obo3 obo2 obo1 obo0 ogo7 ogo6 ogo5 ogo4 ogo3 ogo2 gnd gnd vdd ogo1 ogo0 oro7 oro6 oro5 oro4 oro3 oro2 oro1 oro0 sth8 shc pol hms2 hms1 lp sth1 clkv stv3 stv1 rlsc set gt2 gt1 sxmd pnvd pnhd gnd dclk1 dataht dena vd hd inv vdd gnd gnd obi7 obi6 obi5 obi4 obi3 obi2 obi1 obi0 ogi7 ogi6 ogi5 ogi4 ogi3 ogi2 ogi1 ogi0 ori7 ori6 ori5 ori4 ori3 ori2 ori1 ori0 ebi7 ebi6 ebi5 ebi4 ebi3 ebi2 ebi1 ebi0 gnd gnd obi1 r52 22 r101 22 hms1 v3.3d r60 22 r46 22 r57 22 r87 22 r44 22 r92 22 r36 22 r31 22 ori2 r95 22 r16 22 ebi6 r90 22 r122 22 ogi1 ogi3 r126 22 egi0 r20 22 c2 0.1u r66 22 ebo7 hms2 oro7 ogo4 r97 22 r68 22 r63 22 r54 22 r109 22 v3.3d r42 22 r55 22 r10 22 ego7 ori1 ogo6 obi5 r76 22 r110 22 r35 22 r49 22 r64 22 c6 .1u eri1 scmd r112 22 r2 22 c5 .1u r118 22 v3.3d ogo1 ogi7 r32 22 r18 22

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